This invention relates to a memory access control system adapted for use with a one-chip processor integrally assembled with a direct memory access controller.
In recent years, a microprocessor or central processing unit (CPU) integrated in one chip has become widely accepted as a data-processing system due to enhancements in the development of semiconductor manufacturing techniques. The widespread dissemination of such CPU's has led to the use of a large variety of input-output devices (abbreviated as "I/O devices") with such a computer system. Presently available I/O devices, however, often operate at a higher speed than a processor. Where the I/O device operates at a rate faster than the rate of the processor, it is inefficient to transfer data between the I/O device and the main memory of the computer through the CPU.
To eliminate this drawback, therefore, a direct memory access (abbreviated as "DMA") system has been adopted. A DMA system is designed to effect direct data transfer between the main memory and an I/O device without transferring the data through the CPU, thereby offering the advantages of decreasing the work load on the CPU, elevating data transfer rates, and realizing the quick and efficient processing of data.
Where, however, the DMA system has been adopted in actual practice, the following situation arises. A control system for the practical application of the DMA system includes a system DMA mode for preventing memory access from being effected through the CPU and a system program mode which carries out a memory access on a cycle steal basis wherein a memory accesses through the CPU are alternated with accesses by the DMA. The DMA mode decreases the load on the hardware more than the program mode but results in a lower overall data transfer efficiency.
In contrast, the program mode effects overall data transfer more efficiently than the DMA mode, but requires a data buffer to be provided because of the alternating data transfers by the DMA. Implementation of the program mode further requires an external control circuit to be installed in order to determine whether a request for a memory access is to be undertaken through the CPU or by the DMA. In the past, the time consumed by processing within the control circuit results in added inefficiency, a failure to increase the overall data transfer efficiency to the degree expected, and an increase in the complexity of the hardware arrangement in order to implement the program mode along with the DMA mode.
In order to improve the data transfer efficiency of the program mode, it is necessary to provide a DMA controller (abbreviated as "DMAC") integrally with a CPU, that is, to form both units in a single chip to constitute a large scale integration (abbreviated as "LSI") processor. Such integration enables, for example, the easy transfer of a status command between the CPU and the DMAC in the LSI processor. A further advantage of LSI fabrication is that a request for temporary exclusive use of a memory bus by the CPU or the DMA takes place in the LSI processor and is quickly resolvable. Moreover, the interchangeable use of the memory bus by the CPU or the DMA is attained in an extremely short time by means of the DMAC, thereby greatly increasing the processing efficiency of the processor system.
A need sometimes arises for the selective application of the program mode or the DMA mode according to the instructions of a program in order to process data effectively. However, the installation of an additional external mode-selecting device for control of the above-mentioned selection results not only in an increased load on the operator and the hardware but also in a significant time loss. In the past, the use of an external mode-selecting device has also caused inefficient control of the processor system.